The present invention relates generally to passive buffers and pass gates, and more particularly, to a charge pump circuit, passive buffer that employs the charge pump circuit, and pass gate that employs the charge pump circuit.
Pass Gates
A pass gate is an important circuit element for use in design of digital circuits. There are many applications that utilize pass gates. These applications include, but are not limited to, multiplexers, combinatorial gates, and latches. The pass gate is useful for a designer to selectively allow an input signal to pass or propagate to the output of the pass gate.
FIG. 9 illustrates a prior art full pass gate implemented with an n-type FET and a p-type FET. The full pass gate passes signals when node A is a low logic level and node B is a high logic level. It is noted that two signals (an original and a complement) are needed to control the operation of the full pass gate.
These prior art pass gates have several disadvantages. First, in certain situations, it may not be convenient to generate a complement of an original signal. Second, in many situations, it is desirable for the pass gate to generate an output signal that has a full logic level. When both these situations exist, these prior art pass gates may not be utilized to meet this dual-prong requirement.
Moreover, there are some instances during the design of integrated circuits where it may be desirable for the pass gate to be implemented with a single type of FET in order to simplify or reduce the layout of the circuit or otherwise to meet a space or layout constraint. Unfortunately, the prior art full pass gate requires at least one N-FET and at least one P-FET to operate.
There also exist n-type FET only pass gates and p-type FET only pass gates. The advantage to these types of pass gates is that no complement control signal needs to be generated. The disadvantage is that the n-type FET only pass gates only pass a logic 0 well (e.g., a logic 1 is not fully passed electrically). Similarly, p-type FET only pass gates only pass a logic 1 well (e.g., a logic 0 is not fully passed electrically).
Passive Buffers
A passive buffer (also known as a delay) is an important circuit element for use in design of digital circuits. There are many applications that utilize delays. These applications include, but are not limited to, deracing devices and skew reduction devices. The delay is useful for a designer to create a complement signal based on an original signal.
The complement signal is typically an inverted signal that has a logic level opposite of the original signal. There are two desirable characteristics of the resulting complement signal. First, it is desirable for the complement signal to have the same logic levels as the original signal because typically the application of a signal and its complement are equal in value but opposite in polarity. A full logic level for a signal and its complement is useful in traditional full pass gate structures.
Second, it is desirable for the complement signal to have a minimal amount of skew with respect to the original signal. Skew is defined at a given point (e.g., threshold point) on the signals"" transition (or edge) as the time differences between that given point on two different signals.
FIG. 10 illustrates a prior art inverted delay implemented with an n-type FET and a p-type FET. This prior art passive buffer tends to suffer from the following disadvantage. The inverted delay does not generate a complement signal with a full logic level. Because n-type FET does not pass logic 1 well and p-type FET does not pass logic 0 well, the complement signal has logic levels that are less than the levels of the original signal.
Furthermore, there are some instances during the design of integrated circuits where it may be desirable for the passive buffers to be implemented with a single type of FET in order to simplify or reduce the layout of the circuit or otherwise to meet a space or layout constraint. Unfortunately, the prior art passive buffers do not offer full logic level with a single type of FET.
Based on the foregoing, there remains a need for passive buffers and pass gates that overcome the disadvantages of the prior art as set forth previously.
According to one embodiment of the present invention, a buffer that includes an input node, an output node, and a three-transistor charge pump circuit that is coupled to the input node and the output node is described. The buffer generates an output signal that is a delayed version of a signal presented at the input node. The three-transistor charge pump includes a first transistor that includes a drain electrode that is coupled to the input node, a gate electrode and a source electrode; a second transistor that includes a drain electrode that is coupled to a first predetermined voltage, a gate electrode coupled to the drain electrode of the second transistor, and a source electrode coupled to the gate electrode of the first transistor; and a capacitive element that includes a first electrode that is coupled to the source electrode of the second transistor and the gate electrode of the first transistor and a second electrode that is coupled to the output node.
According to another embodiment of the present invention, a pass gate that includes an input node, an output node, and a charge pump circuit that is coupled to the input node and the output node is described. The charge pump circuit has a fourth transistor (referred to as a control transistor). The control transistor receives a control signal and based thereon selectively enables the first transistor (e.g., the pass transistor) to pass the signal at the input node to the output node. When the control transistor is off, the charge pump circuit behaves as in the passive buffer embodiment, thereby allowing the input to pass to the output at a full logic level. When the control transistor is off, the control transistor drains the charge pump node, thereby disabling the first transistor (e.g., the pass transistor).
Other features and advantages of the present invention will be apparent from the detailed description that follows.